Radio communication apparatuses such as a cell phone often adjust the rate of data to be transmitted in accordance with the transmission environment or the like. Specifically, for example, according to the High Speed Packet Access (HSPA) communication technology standardized by 3rd Generation Partnership Project (3GPP), when transmitting encoded data, a radio communication apparatus applies a rate matching process to the bit sequence obtained after error correction encoding. That is, in error correction according to HSPA, the transmitter generates two parity bits with respect to one information bit by using a turbo code with a coding rate of ⅓. Then, in the rate matching process, the transmitter performs thinning-out of bits (puncturing) from the error correction encoded bit sequence, or performs repeating of bits (repetition), depending on the quality of the propagation path. At the receiver, rate de-matching is performed. Rate-dematching is a reverse process vis-à-vis the rate matching process of the transmitter. Rate de-matching produces a bit sequence upon which the receiver then performs error correction decoding.
In the rate matching process standardized by 3GPP, puncturing or repetition is to be performed by an algorithm using a parameter e used for judgment. That is, for puncturing, a predetermined decrement value eminus is sequentially subtracted from a judgment value e, and if the judgment value e becomes negative upon performing subtraction of the decrement value eminus m times (m is an integer larger than or equal to 1), the m-th bit is punctured, and an increment value eplus is added. For repetition, after subtracting a predetermined decrement value eminus from a judgment value e corresponding to a given bit, if the judgment value e becomes negative, a predetermined increment value eplus is sequentially added to the judgment value e, and until the judgment value e becomes positive, the same bit is repeated every time the increment value eplus is added (refer to 3GPP TS 25.212 V7.10.0, “Multiplexing and channel coding”, 2009-3).
As described above, according to the above algorithm, whether or not a given bit is to be punctured or repeated depends on the judgment value e corresponding to the immediately preceding bit, and whether or not puncturing or repetition is performed is judged sequentially starting from the front bit of a bit sequence. Thus, the number of times a loop process is executed increases, which makes it difficult to make rate matching faster particularly in cases where the size of a transport block is large as in HSPA.
Accordingly, one approach being considered is to divide an inputted bit sequence into a plurality of blocks, calculate the judgment value e for the leading bit of each of blocks, and perform rate matching in parallel between individual blocks (for example, refer to Japanese Laid-open Patent Publication No. 2002-199048).
However, when performing rate matching in parallel, the resulting computations tend to become complex, leading to an increase in the amount of processing and circuit area. In this regard, to calculate the judgment value e for the leading bit of each block, Equation (1) below is used to find a judgment value e(m) for the m-th bit, for example.e(m)=eini−[{eminus(m−1)} mod eplus],m=1,2, . . . ,L  (1)
It should be noted that eini is the initial value of the judgment value e, and L is the size of an inputted bit sequence (i.e. the number of bits). If the judgment value e(m) obtained by Equation (1) is negative, a value obtained by adding an increment value eplus serves as the judgment value e(m). Now, Equation (1) includes modulo operation, and if the value of L is large, the number of digits of bits in the multiplication of eminus and (m−1) becomes large. Since such modulo operation and multiplication are complex computations in comparison to simple addition or subtraction, the amount of processing required for obtaining the judgment value e for the leading bit of a block is large. To perform computations requiring a large amount of processing at high speed, the required circuit area increases.
Another approach also being considered is to perform parallelization of rate matching by obtaining an adjustment value q(m) indicating the number of bits to be punctured or repeated up to the m-th bit by Equation (2) below. Equation (2) also includes division and multiplication, resulting in an increase in the amount of processing and circuit area (for example, refer to Japanese Laid-open Patent Publication No. 2008-311869).
                              q          ⁡                      (            m            )                          =                  ⌈                                                    m                ·                                  e                  minus                                            -                              e                ini                            +              1                                      e              plus                                ⌉                                    (        2        )            